physical design interview questions Part 2/2 51. How will you know that two clocks are synchronous. 52. what is crosstalk.how will you fix. 53. Explain what is setup and hold with waveforms. 54. what is use of filler cells, endcap cells, decaps and metalfill. 55. where we place ICG cell at the port or sink …
physical design interview questions Part 1/2 1. What are the things we consider before doing floorplan, and clock tree synthesis.2. Given with different macro count how will u do the floorplan.3. Different kinds of blockages and how they are used for congestion.4. How we decide the channel space between the macros, and based on the …
1. What are SDC, how do you decide that a path is a false path? 2. What is max transition? How you decide that value? 3. How do you set max output load (based on what factors?) 4. What are the inputs to Prime Time? 5. What does you do for low power design? 6. …
1. How do you calculate maximum frequency given setup, hold, clock and clock skew? 2. Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency? 3. How to solve cross clock timing path? 4. In StarRC, what is “Un-annotated Nets”? …
1. Is NDR better or shielding better for clock tree synthesis? 2. Explain booth’s algorithm for multiplication 3. Design a circuit which outputs a frequency of 2f with an input of f. 4. A, B, C are unsigned 32-bit numbers. How many bits are needed for Y = (A * B) +C? 5. Design a …
1. If you have 10,000 DRC violations on a post-route database, what would be your approach to fix these violations? 2. Design AND, OR and NOT gates using Muxes? 3. How to fix glitch violations? 4. What is Multi-Input-Switching (MIS)? 5. How to margin for MIS in timing constraints? 6. What is a Transition Delay …
1. Setup time equation ?2. Hold time equation ?3. Differences between flop and a latch ? 4. What are different ways to fix a setup time violation ? 5. What are different ways to fix a hold time violation ? 6. What is GBA analysis ? 7. What is the difference between GBA and PBA …
1. What is signal integrity? How it affects Timing?2. What is IR drop? How to avoid .how it affects timing?3. What is EM and it effects?4. What is floor plan and power plan?5. What are types of routing?6. What is a grid .why we need and different types of grids?7. What is core and how …
1. What is MMMC (multi-mode multi corner)?2. What are the guidelines for macro placement?3. What are the sanity checks in pd?4. What is the difference between Halo and Blockage?5. Why we apply NDR rules before routing?6. What are the types of blockages?7. How to fix congestion?8. How will you reduce congestion near I/O ports?9. What …
1. How do you sign-off static IR drop and dynamic IR drop?2. How to minimize addition of hold buffers?3. Write Verilog code for a regular encoder and a priority encoder?4. What is JTAG?5. What is mBIST?6. If you have 10,000 DRC violations on a post-route database, what would be your Approach to fix these violations?7. …