Physical design Interview Questions part-14

1. What are the things we consider before doing floorplan, and clock tree synthesis.
2. Given with different macro count how will u do the floorplan.
3. Different kinds of blockages and how they are used for congestion.
4. How we decide the channel space between the macros, and based on the pins how to place the macros.
5. What do we have in SDC file (complete explanation what we have and why we need them)
6. How congestion occurs and what are the different ways to solve it, and how it effects timing.
7. What kind of issues you faced in your design and how you solved them.
8. What is difference between normal buffers and clock buffers and why we use clock buff's
9. Where we get tran violations and asked to explain with different scenarios, how we fix.
10. With the given time of 10 days how you divide work from floorplan to placement and on what mostly you concentrate.

---------------------{Interviewer asks these below questions too.}---------------------

a. What are the challenges that you have faced during the project.
Depending upon the issues,the questions were went on. They are on Floorplan (macro placement,timing issues).
b. Mostly concentrated on CTS, like how we will balance the skew,what we need to check if the skew is 0ns.
c. what is Antenna effect.and how we can fix them in detail.
d. Why we need to do DRC's.
e. Why we need to do Cell padding. How it will reduce congestion.
f. Asked to explain all the constraints in SDC.
g. Asked about spec.
11. What are the EM challenges faced in your design?
12. What were the design challenges for your block?
13. Given two memories with pins only on one side, which is the best configuration to place such memories during fp?
14. Will you place the memories touching the core where there are IOs?
15. There was a scenario where in they gave a chip size of 10mm X 10mm, with three partitions P1,P2&P3 each of which having a block insertion delay of 1.5ns,1.8ns & 1ns and out of which P2&P3 is frozen. P2 & P3 of size 4mm sitting on top in middle with channels on both the sides and P1 at the bottom left.PLL is on right middle. The design size is approx. 1.8M instances.[Need to estimate the % of flops from that] There is a single PLL and a single clock domain for the whole chip. Also they gave the channel spacing of 0.5u and there were logic placed in all the channels and the placement is frozen.How will I plan the clock tree for the top? I need to build the cts both manually and using the tool. Based on the above scenario below questions were asked
16. what is the first step to do clock tree synthesis?
17. which part of the chip will you manually build the cts for?
18. what considerations will u take while building the cts?
19. What will be the insertion delay for the top?
20. What settings will you use for the cts on the hierarchical block P1,P2& P3
21. Should we build a clock tree with increasing order of drive strength of buffers from root or decreasing order?
22. At the PLL, which drive strength should be used for clock buffer and why?
23. Which clock tree is better, the one with shielding on a single spacing or the one with double spacing?
24. How will you fix crosstalk?
25. How will you fix transition giving a scenario of the placement of the logic.
26. Giving a scenario with io path, reg2reg path, write the SDC for the chip. Assuming the clock frequency or input/output delay for the IO is not known.
27. How will you set the constraints for the clock input pin in the SDC?
28. There is path from the launch clock at 2ns and capture clock at 3ns, where the tool checks the setup and hold? Write the command for hold check in PT?
29. What are the challenges faced in your projects? asked based on the resume.
30. What challenges you faced in floorplan? How did you handle if a block has huge macros.
31. What is crosstalk and how do you fix?
32. Why do we build the clock tree, how do you build it?
33. What are the inputs to build the CTS?
34. What is skew, Global skew and local skew?
35. Given a path from clock port to two sink flops, one path is direct and other path has clock divider circuit in between. In this case how do you build the clock, what are the things to take care?
36. If you move a flop after the CTS, what effects do you find. If there are no setup and hold issues what else timing issue do you find? (expecting clock gating timing violations)
37. How do you fixed the timing violations?
38. Given different scenarios and asked how do you fix the timing violations. (Adding buffers for long nets, upsizing, cloning etc)
39. Given a flop to flop path with clock timeperiod 2ns and 4ns respectively, what are the things to take care, at what edges setup and hold checks done.
40. If you have a flop to flop path with asynchronous clocks, how do you handle it?
41. What are SDC constraints you give for a feed through paths and flop to flop paths of a block. Specific about the technology and design constraints.
42. Current Projects: Responsibilities and issues.
43. Basic PD Flow?
44. what are initial checks you do and what will happen if you have any issues.Reasons for why design should not have these. example (What will happen if you have floating input pins).
45. Is it ok to have floating output pins. and is it ok if you have a cell which is not connected to input or output.
46. Before going to floorplan what will you check.
47. If you have a 1000 macros how will start floorplanning.
48. Congestion techniques
49. Which one you will fix during placement, setup, tran and hold? why you dont fix hold during the placement.
50. What you will do exactly in CTS. he is asking about scenarios like if you build a clock tree whose frequency is 500Mhz. after postCTS clk freq is 1GHz, will you continue with same clock tree or rebuild it.