51. How will you know that two clocks are synchronous.
52. what is crosstalk.how will you fix.
53. Explain what is setup and hold with waveforms.
54. what is use of filler cells, endcap cells, decaps and metalfill.
55. where we place ICG cell at the port or sink and why? you have 10 clocks in your design frequency ranging from 100Mhz to 1GHz, for these clocks where you place ICG?
56. What is OCV? What is CRPR?
57. what are DRCs you have seen in your design.
58. He gave different scenarios in floorplanning, Timing and CTS. How will you do?
1. Current projects - responsibilities : This is Resume related so prepare well and keep data handy
2. Multi-voltage concepts
3. What are the considerations and proper way to partition a multi-voltage design, identifying proper power domains
4. STA complexity in sub-nm and multivoltage designs, STA complexity in hierarchical design
5. What all are the way to minimize STA corners in the top level for a hierarchical design (one ans he is looking for to push pipeline flops inside blocks to reduce top level timing paths)
6. Multi-VT - how do you explain phenomenon and effects to a fresher
7. He asked about SI Prevention in the flow from Placement to Routing .Steps need to take care
8. What is the difference between MMMC & normal flow.If a design is given to implement what are the pros & cons of it .
9. What is temperature inversion corner.How do we come up with derate values for a particular corner(factors deciding the derats like 6% or 10%)
10. What are the criterias for Scan stitching in synthesis .If we reorder scan chain during P & R does it disturb the Testability vectors
11. What are DFM issues & how do we attack it during the flow .Can you name some which was not there in 90nm but was seen in 45nm to great extent (He was expecting well proximity check & Latch up )
12. How do we pick up MCMM corners during P & R for Setup & hold corners.Factors deciding the corners.
13. Internal Structure of a Tie High & Tie Low cell.Why dont we connect standard cells directly to VDD & VSS.Pros & cons of it
14. How do we come up with Timing ECO's without any discripency for a huge database
15. Discussion on any topic is totally depend on our Projects in resume & also he is looking at the approaches how do we attack a situation.He is cool & friendly during the discussions
16. How do you debug LVS error?
17. What kind of LVS errors do i have seen.
18. Any significant change from 90nm to 65nm in tems of library configuration.
19. Discussion regarding nwell latchup and hot nwell drc.
Discussion regarding nwell latchup and hot nwell drc.
20. Details about latest project as it was custom designed,he was more interested.
21. What is Temparature inversion and why?
22. What is ICG and its pros and cons?
23. What is OCV?what are the factors for OCV?
24. What is crosstalk and what are all possible fixes?
25. What are main(worst) issue that I have faced in all the projects and resolutions that I have made to fix.
Detailed questions on congestion as I have told congestion as answer for the above question
a. why congestion happened(what are the reasons)
b. What are all possible reasons for congestion
c. What are the solutions?
Details about last project and issues faced in that ?
26. What is ICG and How it will be helpful ?
27. where do we place ICG ?
28. what is crosstalk and it will impact our design?
29. how can we avoid crosstalk?
30. What consern about sheilding?
31. what are corners that you have used to close timing ?
32. What is temperature invertion ?
33. what is input delay and output delay?how cts impacts on io paths?
34. Details about previous project and issues faced in that.
35. Clock gating violations and how to fix
36. What is temp inversion? And what is it dependent on?
37. Giving example he asked how OCV effects could be reduced between clock trees going to 2 separate blocks from top level
38. Giving example he asked what could be done to improve floorplan and pin placement for an irregular shaped block
39. what are different corners in ur design?
40. What are the checks you do after the placement
59. What are all you take care while building clock tree
60. What will be the difference if you build clock tree with buffers & inverters
61. What is transition how you decide the threshold value for transition
62. What are the checks after routing
63. Define set up and hold time, 3 ways of fixing setup violations if slack is -400ps
64. What is OCV , how you consider derate values for setup checks
65. What is the use of applying non default rule to clock path
66. How good you are at Aprisa and STA tools and can you understand timing report
67. What are the params in aprisa to manipulate hold
68. Have you aware of the things inside the .proj / directory
69. How you fix hold violations in aprisa
70. How you fix clock transition violations?
71. What is NDR?
72. Why are you using double width ?
73. if space between the wires is same and double the width then what happens to the resistance and capacitance?
74. What is OCV? Example
75 What is CRPR?
76. If clock net in common path is affected by noise then will the delay be subtracted by CRPR?
77. When are you scenarios in your flow?
78. What input will you give for scenario creation?
79. How do you give the ECO file in your flow? No of cells on avg
80. What is multicycle path ? If there is a design with launch 5ns and capture 10ns then how will it work ?
81. What were the different constraint issues that you faced in your design?
82. Challenges faced in your previous projects?
83. Why do you use tap cells in design?
84. Internal structure of Tap cells. What is connected to what ?
85. What is Clock gating violations? how to fix them?
86. How will you approach script for making a ring of M2 around a ram with some offset?
87. you had a crosstalk problem , if you were to redo the floorplan then what changes would you make?
88. What are the input spec to CTS?
89. Why are clock inverters better than clock bufers?
90. What is the difference between a normal buffer and clock buffer?
91. How do clock buffers have equal rise and fall time? why is it important?
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