Physical Design Interview Questions 1
Make a career in vlsi physical design domain
- How will you make sure that your power structure is good?
- Why we are following certain guidelines for macros placement and what are those guidelines?
- What is the minimum space required between macros if channel is in non-pin side of macros?
- What is the distance between tap cells in your design?
- How will you perform cell spreading in placement if congestion is there?
- Tell me about 2-pass approach in placement.
- Why we are not taking care about hold violations at placement stage?
- What are the difference between OCV and POCV?
- What are the different ways to fix setup and hold? Which one is difficult to fix setup? or hold?
- Which violation will you fix first, Setup? or Hold?
- How will you improve your insertion delay?
- What happens if you place macros at the center?
- If there is a situation that you have to place the macro at the center?
- Issues you face in placement stage? and How do you fix them?
- What will you check setup in placement stage and why will you check hold after CTS?
- Placement optimization techniques?
- Write setup and Hold equations?
- Techniques to fix Setup and Hold?
- If you have to optimize the design but still you have setup violations how will you fix them?
- What is CTS?
- What is clock tree specification file?
- How do you know the time slack is acceptable to go next stage?
- what does def file consists of?
- What does LEF file consists of?
- What is crosstalk?
- What are NDR rules? Why we need to apply NDR rules?
- What is difference between clock buffer and normal buffer?
- Buffer or inverter which one is preferable for CTS?
- What is Latency?
- What are the inputs for LVS?
- What is metal pitch?
- What is multi Cycle Path?
- What is OCV and AOCV?
- Do you Know anything about DPT?
- What are the contents of SDC file?
- If one path have both setup and hold violations? How will you fix that path?
- Do you know about negative skew and positive skew? Briefly can you tell about that?
- What is the difference between flat cells and hierarchical cells?
- What is more complicated when you hace a 48 MHz and 500 MHz clock design?
- How do you place macros in a full chip design?
- What are the parameters or aspects to differentiate Chip design and Block level design?
- If the routing congestion exists between two macros, then what will you do?
- If Lengthy mental layer is connected to diffusion and poly, then which one will affect by antenna problem?
- How to calculate core ring width, macro ring width and strap or trunk width?
- How to find number of power pad and IO power pads?
- How the width of metal and number of straps calculated for power and ground?
- What are the problems faced related to timing?
- During power analysis, if you are facing IR drop problem, then how did you avoid?
- Define antenna problem and how do you resolve this problem?
- How delays vary with different PVT conditions? show the graph?
Join us for your dream job in VLSI Domain as Physical Design Engineer. We in VLSI Mentors work for your career progression. Our mission is to give you the best transformation from basic engineering to a well professional VLSI engineer. Here with us you can gain experience in latest technology nodes with hands on work in Latest EDA tools in Block level or Full Chip design.
These interview questions are part of Job selection process. Your Interview preparation starts from this step. Enroll with us for complete skill development in Physical Design and land in a VLSI domain roles to kick start your career.
Beginner or professional you can always contact us for your career in VLSI design and enroll with us.